1.文件的准备
先clone到库到本地：
git clone https://github.com/riscv-mcu/e203_hbirdv2.git
有时候提示连不到 ，可以试下http://这样地址
正克隆到 'e203_hbirdv2'... remote: Enumerating objects: 1487, done. remote: Counting objects: 100% (105/105), done. remote: Compressing objects: 100% (48/48), done. remote: Total 1487 (delta 69), reused 57 (delta 57), pack-reused 1382 (from 2) 接收对象中: 100% (1487/1487), 62.38 MiB | 457.00 KiB/s, done. 处理 delta 中: 100% (717/717), done. Checking out files: 100% (1050/1050), done.
文件介绍：
. ├── doc │ ├── Makefile │ ├── requirements.txt │ └── source ├── e203_core.core ├── e203_soc.core ├── fpga │ ├── common.mk │ ├── ddr200t │ ├── Makefile │ ├── mcu200t │ └── README.md ├── LICENSE ├── pics │ ├── DDR200T.JPG │ ├── debugger.JPG │ ├── hbirdv2_soc.JPG │ └── MCU200T.JPG ├── README.md ├── riscv-tools │ ├── build.common │ ├── build-e203-rvtests.sh │ ├── fpga_test4sim │ ├── README.md │ └── riscv-tests ├── rtl │ └── e203 ├── tb │ └── tb_top.v └── vsim
目录结构如上图，可以看到
vsim ：仿真目录，仿真脚本Makefile等；
tb：测试仿真文件
rtl:核和soc代码
doc:参考文档 可以转换为html格式
2.Download RISC-V GNU toolchain from Nuclei Download Center.
下载这个版本 其他版本类似nuclei_riscv_newlibc_prebuilt_linux64_2022.08.tar.bz2
解压缩：
[....]$tar -xjvf nuclei_riscv_newlibc_prebuilt_linux64_2022.08.tar.bz2 gcc/ gcc/lib/ gcc/lib/gcc/ gcc/lib/gcc/riscv-nuclei-elf/ gcc/lib/gcc/riscv-nuclei-elf/10.2.0/ gcc/lib/gcc/riscv-nuclei-elf/10.2.0/rv64imafdcb/ gcc/lib/gcc/riscv-nuclei-elf/10.2.0/rv64imafdcb/lp64d/ gcc/lib/gcc/riscv-nuclei-elf/10.2.0/rv64imafdcb/lp64d/crti.o gcc/lib/gcc/riscv-nuclei-elf/10.2.0/rv64imafdcb/lp64d/crtbegin.o gcc/lib/gcc/riscv-nuclei-elf/10.2.0/rv64imafdcb/lp64d/libgcc.a gcc/lib/gcc/riscv-nuclei-elf/10.2.0/rv64imafdcb/lp64d/crtn.o gcc/lib/gcc/riscv-nuclei-elf/10.2.0/rv64imafdcb/lp64d/crtend.o gcc/lib/gcc/riscv-nuclei-elf/10.2.0/rv64imafdcb/lp64d/libgcov.a gcc/lib/gcc/riscv-nuclei-elf/10.2.0/install-tools/ .....
进入我们的e203项目目录，创建目录：
cd e203_hbirdv2 mkdir -p ./riscv-tools/prebuilt_tools/prefix/bin cd ./riscv-tools/prebuilt_tools/prefix/bin/ ln -s /gcc/bin/* . #这里是解压后的gcc目录
接下来编译测试用例：
cd e203_hbirdv2/riscv-tools/riscv-tests/isa source regen.sh
这个.sh文件就是执行makefile命令 regen.sh 内容如下
make -C generated -f ../Makefile src_dir=../ XLEN=32
先切换到 generated 目录再执行后续命令 目的是 编译汇编测试成，反汇编生成(.dump文件) ，生成的.verilog文件，地址重映射;
3.接下来准备跑仿真：
1.编译rtl
cd e203_hbirdv2/vsim make clean make install // For VCS: make compile SIM=vcs // For iVerilog: make compile SIM=iverilog
2.run默认case
// For VCS: make run_test SIM=vcs // For iVerilog: make run_test SIM=iverilog
最后输出仿真结果：
NOTE: automatic random seed used: 4086908620
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
TESTCASE= /home/xxxxx/e203_hbirdv2/vsim/run/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p-add
VCS used
*Verdi* Loading libsscore_vcs201809.so
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
(C) 1996 - 2019 by Synopsys, Inc.
*Verdi* : Create FSDB file 'tb_top.fsdb'
*Verdi* : Begin traversing the scope (tb_top), layer (0).
*Verdi* : Enable +mda dumping.
*Verdi* : End of traversing.
ITCM 0x00: 340510730001a225
ITCM 0x01: ff85051300002517
ITCM 0x02: 01f5222301e52023
ITCM 0x03: 020f4f6334202f73
ITCM 0x04: 4fa505ff0d634fa1
ITCM 0x05: 07634fad05ff0a63
ITCM 0x06: 0bff00634f8505ff
ITCM 0x07: 4f9d0bff0b634f95
ITCM 0x16: 3400257300452f83
ITCM 0x20: 3400257334302573
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~ Test Result Summary ~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~TESTCASE: /home/xxxxxx/e203_hbirdv2/vsim/run/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p-add ~~~~~~~~~~~~~
~~~~~~~~~~~~~~Total cycle_count value: 25857 ~~~~~~~~~~~~~
~~~~~~~~~~The valid Instruction Count: 16577 ~~~~~~~~~~~~~
~~~~~The test ending reached at cycle: 25817 ~~~~~~~~~~~~~
~~~~~~~~~~~~~~~The final x3 Reg value: 1 ~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~ ##### ## #### #### ~~~~~~~~~~~~~~~~
~~~~~~~~~ # # # # # # ~~~~~~~~~~~~~~~~
~~~~~~~~~ # # # # #### #### ~~~~~~~~~~~~~~~~
~~~~~~~~~ ##### ###### # #~~~~~~~~~~~~~~~~
~~~~~~~~~ # # # # # # #~~~~~~~~~~~~~~~~
~~~~~~~~~ # # # #### #### ~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
$finish called from file "/home/xxxxxx/e203_hbirdv2/vsim/run/../install/tb/tb_top.v", line 222.
$finish at simulation time 10355800
V C S S i m u l a t i o n R e p o r t
Time: 103558000 ps
CPU Time: 8.290 seconds; Data structure size: 2.6Mb
注意：“The final x3 Reg value: 1” 这个是我们程序里设置的判断结果 如果TEST_PASS 就设置x3寄存器的值为1，而在TEST_FAIL处 程序讲X3寄存器设置为非1值，从而通过x3寄存器的值判断运行结果是成功还是失败。 x3即：
u_e203_soc_top.u_e203_subsys_top.u_e203_subsys_main.u_e203_cpu_top.u_e203_cpu.u_e203_core.u_e203_exu.u_e203_exu_regfile.rf_r[3];
查看仿真波形：
// Using Verdi: make wave SIM=vcs // Using GTKWave: make wave SIM=iverilog
其他的比如跑回归：
// For VCS: make regress_run SIM=vcs // For iVerilog: make regress_run SIM=iverilog